Dancin' with the Devil

Just about every review site has taken a unique approach to motherboard testing at one time or another, especially when it comes to overclocking. Over the last few months, we have taken a slightly different approach with the performance-oriented motherboards by offering additional technical information and a few BIOS guides to help end-users set up the ever more complicated BIOS functions that are available on today's boards. Our primary directive is to ensure everything we achieve in the cozy confines of the labs is fully repeatable with the same off-the-shelf retail components and settings.

The basic test criteria we use when overclocking the Intel enthusiast boards is setting FSB speeds in the 400-465FSB region. We ensure tRD is set as low as possible while keeping component voltages to a minimum level for stable long-term use. This type of overclocking might not sound very sexy - Patrick Swayze would dump us fast for not doing the Argentine tango with high FSB rates. However, our recent forays into dissecting DDR2 and DDR3-based motherboard overclocking have shown that tRD (Read Delay) is the most important tunable BIOS option available to the overclocker when seeking measureable performance improvements when overclocking Core 2 processors.

Those who wish to increase their insight or review just what the Northbridge strap setting and tRD are, how they both work, and why we are enamored with these settings are advised to read this article first and parse through this one for additional background information. Most overclockers are thoroughly aware that increasing processor voltage is required to allow speed scaling, but may fail to realize that raising MCH voltage is necessary when using a higher processor multiplier. The primary reason is to cope with the additional data throughput via the chipset busses as FSB levels rise.

Early implementations of the P965 chipset allowed FSB scaling to reach levels that were unheard of (in conjunction with the Core 2 Duo) by increasing the overall chipset latency at certain FSB points. Quite often, the deficit in chipset latencies at higher FSB speeds was enough to nullify a processor core speed increase of 100Mhz or more - meaning that a higher FSB overclock would trail the performance of a lower CPU speed using a lower FSB and higher CPU multiplier (due to Northbridge strap latency changes). It was not until the P965 was about to be replaced by the P35 that we finally began to see the release of high performance 965 boards - namely the Abit Quad GT and the DFI P965-S "Dark". These boards locked the 1066 Northbridge strap, while allowing Front Side Bus speeds near or above 500FSB that retained linear performance scaling to some degree.

To date, we have noticed that properly tuned Intel P35/X38/X48 chipsets also feature near linear performance scaling as FSB speeds rise. In fact, although NB strap changes are available manually, the straps really do nothing at this point but allow the use of different memory dividers. We are finding that increases in Northbridge voltages between a 6x and 7x multiplier may not be huge if even needed, but when we step over to the 8x multiplier (at equivalent settings) we have noticed a major jump is usually required in VMCH to hold the applied overclock "stable".

This is true even on the latest top-end motherboards featuring the X38/X48 chipsets. Therefore, using an 8X or 9X multiplier to show a high FSB holds more merit to the board and CPU capabilities than using a 6X multiplier to show off a board's high FSB capabilities. If a board can achieve a high stable FSB with a higher multiplier, it makes sense that a lower multiplier will have no problem achieving the same or greater FSB speeds.

For the seasoned overclocker nothing we have said above is anything new or groundbreaking. Our main goal though is to remain realistic for our readers, so that we show what is really possible rather than something that can only be held together with chewing gum and sticky tape for 5 minutes for that impressive SuperPi 1M screenshot.

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